A conventional computer system includes a processor that retrieves or reads program instructions from a memory system through a memory controller and executes the program instructions to perform a corresponding function. The processor also transfers data to and from the memory system via the controller during execution of the program instructions. The amount of data and program instructions that are transferred between the processor and the memory system in a specified amount of time is known as the throughput of the memory system. The higher the throughput of the memory system, the faster the processor executes a particular program and thus the faster the operation of the computer system.
FIG. 1 illustrates a portion of a conventional memory system 100 including a memory controller 102 coupled to a memory 104 over a data bus DQ, an address bus ADDR, and a control bus CONT. The memory 104 includes four memory modules 106–112, each memory module including a plurality of memory devices 114 which, in turn, each includes four memory banks B1–B4. Each memory bank B1–B4 includes a plurality of memory cells (not shown) arranged in rows and columns, as will be understood by those skilled in the art. In the example of FIG. 1, each memory module 106–112 receives two corresponding chip select signals CS1#–CS8# from the memory controller 102 over the CONT bus, with the memory devices 114 on each module receiving one of the two applied chip select signals. A group of memory devices 114 on a memory module 106–112 that receive the same chip select signal CS1#–CS8# is known as a rank of memory, with the memory modules 104 collectively including eight ranks R1–R8 that receive the chip select signals CS1#–CS8#, respectively. E04, each memory module 106–112 contains two ranks of memory defined by two groups of memory devices 114 on the module that receive one of the two applied chip select signals CS1#–CS8#.
The operation of the memory system 100 during read operations will now be described in more detail with reference to the signal timing diagram of FIG. 2. In operation, the memory controller 102 applies a command to the memory modules 106–112 in the form of address signals on the address bus ADDR and control signals 116 along with the chip select signals CS1#–CS8# on the control bus CONT. The memory controller 102 activates only one chip select signal CS1#–CS8# at a time and only the rank receiving the activated chip select signal response to be applied command. At a time T1, the memory controller 102 initially applies a row or active command ACT including specific row and bank addresses to access a specific row in a specific bank in a specific rank of memory. In the example of FIG. 2, the memory controller 102 applies an ACT command to activate rank R1 (the group of memory devices 114 on the memory module 106 coupled to chip select CS1#), bank B1, and row R1. The memory controller 102 thereafter applies a burst read command RD at a time T2 to address specific memory cells in the activated or opened row R1. At a time T3, the memory devices 114 in rank R1 place a first data word DW11 on the data bus DQ in response to the burst read command RD applied at the time T2. As will be appreciated by those skilled in the art, in response to the burst read command RD the memory devices 114 sequentially output a series or burst of data words on the data bus DQ. In the example of FIG. 2, the burst length is 4 and thus data words DW11, DW12, DW13, and DW14 are output from rank R1 at times T3, T4, T5, and T6, respectively, in response to the single burst read command RD applied at time T2.
The period from the times T1–T3 corresponds to the latency of the memory devices 114, which is the delay from when an ACT command is first applied to the memory devices until a first data word DW from the activated row is provided on the data bus DQ. The latency lowers the throughput on the data bus DQ since no data is transferred over the data bus from the times T1–T3. To eliminate the adverse effects of the latency on the throughput of the memory 104, and to efficiently use the data bus DQ (i.e. high bandwidth or memory bus efficiency) the memory controller 102 applies a new ACT and RD commands to one of the other ranks R2–R8 or another bank B2–B4 within the rank R1 while the rank R1 supplies the data words DW11–DW14 on the data bus DQ in response to the first burst read command RD at time T2. Thus, at the time T3 the memory controller 102 applies a second burst read command RD to activate rank R2 (the group of memory devices 114 on the memory module 106 coupled to chip select CS2#), bank B1, and row R1. The memory controller 102 thereafter applies a second burst read command RD at the time T5 to address specific memory cells in the activated row R1 in bank B1, rank R2. At a time T7, the memory devices 114 in rank R2 place a first data word DW21 on the data bus DQ in response to the second burst read command RD applied at the time T5, and successive data words DW22, DW23, DW24 at times T8, T9, and T10, respectively.
The memory controller 102 continues operating in this manner to apply ACT and RD commands to open new rows of memory cells in new memory banks B1–B4 in the ranks R1–R8 while data word DW from prior ACT and RD commands is being placed on the data bus DQ. If the burst length is 4 as in FIG. 2, the memory controller 102 is able to hide the latency of the memory devices 114 and increase the throughput of the memory 104 by accessing the memory 104 in this manner. The memory controller 102 continues applying ACT, RD commands to open new rows in new memory banks B1–B4 until all memory banks have been accessed. In the example of FIG. 2, the memory 104 includes 8 ranks R1–R8, each including four banks B1–B4 for a total of 32 banks that can be activated by the controller. After accessing data in each of the 32 banks, the memory controller 102 must begin closing the open rows in each of the banks and accessing new rows to continue reading data words DW from the memory 104. This is true assuming that subsequent accesses are “page misses,” meaning that the subsequent access are to memory cells contained a row other than the open row the banks.
At a time T14, the memory controller 102 applies a precharge command PRE to close the open row R1 in bank B1 in rank R1. In the response to the PRE command, the corresponding memory devices 114 deactivate or close the currently open row, and charge nodes and reset circuits in the memory device in anticipation of a next row being opened, as will be understood by those skilled in the art. In the following description, the term precharge will be used to mean a respective bank B1–B4 in a selected rank R1–R8 closes the currently open row, charges appropriate nodes, and resets appropriate circuits to thereby place the bank in condition to open a subsequent row. Because the memory controller 102 must now apply PRE commands to the memory 104, the flow of data words DW on the data bus DQ is interrupted, lowering the throughput of the memory system. This is true because the memory controller 102 is unable to apply consecutive ACT, RD commands at the required times to maintain a continuous flow of data words DW on the data bus DQ due to the need to begin applying precharge commands PRE to the memory 104. Thus, the data bus DQ efficiency drops because the system is command bandwidth limited.
As illustrated in FIG. 2, the memory controller 102 applies the PRE command at the time T14 and must thereafter wait a row precharge time TRP before applying a new ACT command to the rank R1 at a time T15. While the PRE command at time T14 can be applied early enough to eliminate or “hide” the row precharge time TRP and latency of rank R1, bank B1, a gap during which no data words DW are placed on the data bus DQ will still appear due to the PRE command. This gap is illustrated in FIG. 2 between a time T16 at which the final data word DW324 is placed on the data bus DQ and a time T17 at which the final data word DW from rank R1 is placed on the data bus. There are no data words DW on the data bus DQ from the time T16 until the time T17, and such a gap occurs on the data bus DQ for each of the ranks R1–R8.
To eliminate the need of applying a separate precharge command PRE to precharge banks within the memory 104, a read-auto precharge command RD-AP was developed. The RD-AP command is a separate command that may be applied by the memory controller 102 instead of the standard read command RD. In response to the RD-AP command, the memory 104 automatically precharges a corresponding bank unless another read command RD or a write command WR is applied to the bank within a column-to-column delay time TCCD, as will now be explained in more detail with reference to FIG. 3. FIG. 3 is a signal timing diagram illustrating the operation of the memory 104 where the memory system is adapted to receive RD-AP commands. The memory 104 whose operation is illustrated in FIG. 3 is a synchronous system and thus a clock signal CK is shown. At times T1 and T2, the memory controller 102 applies ACT and RD-AP commands, respectively, to a selected bank B1–B4 and rank R1–R8 in the memory 104, and at a time T3 the memory controller applies a standard read command RD to the selected bank to access different columns of memory cells within the opened row. The standard RD command corresponds to a “page hit,” meaning the controller 102 accesses different columns in the open row or “page” of memory cells. The memory controller 102 applies the RD command within the time TCCD of the RD-AP command, and thus no precharge is performed at this point even though the memory controller has apply the RD-AP command. At times T4 and T5 bursts of data words DW are applied on the data bus DQ responsive to the RD-AP and RD commands, respectively.
The column-to-column delay time TCCD occurs at a time T6 after the RD command is applied at the time T3, and at this point the memory controller 102 fails to apply another RD command or a write command WR to the selected bank B1–B4, rank R1–R8. As a result, the memory devices 114 in the selected bank B1–B4 automatically precharge so that this bank is ready to open a new row in response to a subsequent ACT command from the memory controller 102. In this way, each of the 32 banks B1–B4 in the ranks R1–R8 automatically precharge without requiring the memory controller 102 to supply a separate PRE command to the bank, which improves the throughput of the memory 104 by reducing periods during which no data words DW may be placed on the data bus DQ. The RD-AP command places the selected bank B1–B4 and rank R1–R8 in what is known as a persistent auto precharge mode of operation, meaning that after the RD-AP command is applied the bank will be precharged automatically (the precharge “persists”) unless the precharge is “held off” or delayed by applying a RD or WR command within the time TCCD. While the separate RD-AP and WR-AP command approach eliminates the need to apply a separate PRE command to the memory 104, two additional commands in the form of the RD-AP and WR-AP commands are nonetheless required and must be applied at appropriate times to increase the throughput of the memory system as desired. These factors increase the overall complexity of the memory 104 described with reference to FIG. 3.
Another approach that eliminates the need to apply separate precharge PRE and read auto-precharge RD-AP commands is illustrated in the timing diagram of FIG. 4 which shows the operation of the memory 104 where the memory system 100 utilizes persistent auto precharge to automatically precharge banks B1–B4 of the memory system. In the memory system 100 whose operation is illustrated in FIG. 4, each RD command places the selected bank B1–B4 and rank R1–R8 in a persistent auto precharge mode, and unless another read RD or write WR command is applied within the column-to-column delay time TCCD the bank is precharged. The system 100 operates in the same manner as described with reference to FIG. 3, except no separate RD-AP command need be applied to place the memory 104 in the persistent auto precharge mode of operation. At the time T6, which occurs the time TCCD occurs after the RD command is applied at the time T3, no RD or write command WR is applied to the selected bank B1–B4 and rank R1–R8, and thus the selected bank precharges automatically. With this approach, no separate precharge PRE or read auto precharge RD-AP command is required, which once again improves the throughput of the memory 104 by reducing periods during which no data words DW may be placed on the data bus DQ for the same reasons discussed above with reference to FIG. 3.
Some applications, like graphics applications or transferring data to and from a mass storage device like a hard disk, include a lot of page hits, meaning the memory controller 102 accesses multiple addresses in each open row or page. In contrast, some applications, such as server applications, typically access single addresses in each open row. The persistent auto precharge methodology was developed to allow the same memory 104 to be utilized in both types of applications: auto precharge can be delayed in graphics-type applications to keep pages open and pages can be automatically closed in server-type applications. While the persistent auto precharge methodologies described with reference to FIGS. 3 and 4 improve throughput in some applications, both approaches result in a lower throughput when used in applications requiring error checking and correction (ECC) which, in turn, requires read-modify-write operations be performed, as will now be explained in more detail. In a memory 104 including ECC, the data bus DQ may, for example, be 72 bits wide with eight bits or one byte being an ECC byte and 64 bits corresponding to a data word DW. For example, each bit in the ECC byte could be a parity bit for a corresponding one of the eight bytes in the 64-bit data word. The memory controller 102 performs read-modify-write operations to change only selected bytes of data in the 64-bit data word DW and store this modified data in the memory 104. For example, the memory controller 102 may need to modify only six of the eight bytes in a particular 64-bit data word DW. To modify these six bytes, the memory controller 102 reads the 64-bit data word DW along with the 8-bit ECC byte and combines the six new bytes with the two old bytes to form a new 64-bit data word DW. The memory controller 102 recalculates the value of the ECC byte for the new data word DW and writes the new 64-bit data word along with the new ECC byte back to the memory 104. The time the memory controller 102 requires to read data word DW and ECC byte, merge the old and new data bytes to form a new data word, and recalculate the ECC byte is longer than the column-to-column delay time TCCD. As a result, if a RD command (FIG. 4 system) or RD-AP command (FIG. 3 system) is applied to a selected bank B1–B4 and rank R1–R8, the selected bank will precharge before the memory controller 102 is able to write the modified data word DW back into the open row. The memory controller 102 must therefore apply a new ACT command to once again open the same row in the selected bank B1–B4 and rank R1–R8, which results in a delay in the operation of the memory system 100 while the memory controller waits for the selected row to be reopened. This delay lowers the throughput of the memory 104.
There is a need for a memory system that provides persistent auto precharge features while also allowing read-modify-write operations to be efficiently performed.